1. Field of the Invention
The invention generally relates to clock generators, and more particularly, to a multi-stage delay lock loop for clock phase alignment.
2. Description of the Prior Art
Clock signals are used in virtually every integrated circuit (IC) to control the operational timing of the IC and/or the transfer of data within and between ICs. For example, all individual circuits or devices, such as, for example, flip-flops and/or latches, in a given IC may change state on a single rising or falling edge of a common clock signal. Relatively large ICs, such as, for example, memory chips, programmable logic arrays, or any other IC that requires clock skew adjustment, include thousands or even millions of such individual circuits or devices. The clock signal is typically applied to a clock input pin of the IC for distribution to each of those numerous devices throughout the IC. Thus, the clock signal is transmitted or propagated from the clock input pin to devices on the IC that are both relatively near to and relatively distant from the clock input pin. By the time the clock signal reaches the devices that are disposed on portions of the IC that are relatively remote from the input pin, the clock signal is likely to have suffered significant propagation delay.
The clock signal received at the IC clock input is hereinafter referred to as the input or reference clock signal REF_CLK, whereas the clock signal received by the last-served device on the IC is hereinafter referred to as the feedback clock signal FEED_CLK. The propagation delay between the REF_CLK and FEED_CLK signals, may cause difficulties in interfacing between ICs and/or slow down the overall operating speed of a system. For example, data may be provided or input to an IC in a time-aligned manner relative to the reference clock signal, whereas data output from the IC is likely to be provided in a time-aligned manner with the feedback clock signal.
The propagation delay for a particular IC is dependent at least in part upon the configuration of that particular IC. Thus, for a given IC operating at standard or rated operating conditions, temperatures, and voltages, delay will generally not vary substantially. However, delay will vary due to external factors, such as, for example, changes in ambient temperature, package temperature, and/or applied voltage. It is beneficial to compensate for the effect of such external factors on the propagation delay of the reference clock signal by aligning in time the feedback clock signal FEED_CLK of an IC with the reference clock signal REF_CLK. Delay lock loop circuits are one way in which such time alignment of signals is performed.
Delay lock loop (DLL) circuits receive the reference clock signal REF_CLK and produce an output clock signal CLK_OUT that is advanced or delayed relative to the reference clock signal REF_CLK. For convenience, all signals produced by a DLL will hereinafter be referred to as being delayed relative to the REF_CLK signal regardless of whether the particular signal is actually advanced or delayed relative to the reference clock signal. A DLL delays the output clock signal CLK_OUT by an amount of time that is approximately equal to the propagation delay of the IC, i.e., the amount of time required for the reference clock signal REF_CLK to propagate through the IC under standard or normal operating conditions. Further, a DLL adjusts the CLK_OUT signal to compensate for changes in delay due to the aforementioned external factors. Devices formed on portions of the IC that are proximate to the clock input pin are typically supplied with the REF_CLK signal, whereas devices formed on portions of the IC relatively distant from the input clock signal are typically supplied with the CLK_OUT signal. Thus, all devices on the IC receive clock signals that are aligned in time.
The DLL adjusts the amount of time by which the CLK_OUT signal is delayed relative to the REF_CLK signal by comparing the REF_CLK signal to a feedback clock signal FB_CLK. The FB_CLK signal is essentially a delayed version of the CLK_OUT signal. The FB_CLK signal is delayed by a feedback delay circuit that models the propagation delay through an integrated circuit. The time delay of the FB_CLK signal relative to the CLK_OUT signal is, for example, proportional or equal to the propagation delay of the IC under the predefined operating conditions. As the external factors affect the propagation delay through the IC, they also affect the time delay introduced by the feedback delay circuit.
The CLK_OUT signal is essentially a delayed version of the REF_CLK signal. The delay of the CLK_OUT signal is adjusted by a forward delay circuit having a forward delay line, such as, for example, a predetermined number of buffers or invertors connected together in series. The length of the forward delay line is adjusted based upon a comparison of the REF_CLK signal to the feedback clock signal FB_CLK, to thereby adjust the delay of the CLK_OUT signal and to align in time the CLK_OUT signal to the REF_CLK signal at the end of the clock tree. Thus, changes in the propagation delay due to the external factors are compensated for and the clock signals are time-aligned across a range of operating conditions and parameters.
In designing DLLs, a tradeoff between conflicting design goals has heretofore been required. The first design goal of a conventional DLL is to provide a maximum delay time approximately equal to the longest anticipated cycle time (i.e., the lowest operating frequency) of the REF_CLK signal to ensure alignment under worst-case operating conditions. The second design goal is to provide high resolution, i.e., small time increments, in the adjustment of the delay of the CLK_OUT signal, to maximize alignment of the clocks and, therefore, the operating speed of the IC. Satisfying both of those goals results in a DLL that requires a delay line with a large multitude of delay stages. A large multitude of delay stage new lots of controlling wire and complex controlling method..
Therefore, what is needed in the art is a DLL that achieves a relatively high resolution with relatively few controlling lines. Furthermore, what is needed in the art is a DLL that requires a small number of programming bits. Moreover, what is needed in the art is a DLL that allows a tunable sensing window for fast locking of clock phase.